Scalable Sequential Verification

In general, sequential verification is PSPACE complete, but for application to present-day industrial designs, it needs to be made scalable, which means essentially linear in circuit size. This paper focuses on the problem where the circuit in question has been transformed using a form of scalable sequential synthesis. During this synthesis, a history And-Inverter-Graph (HAIG) is constructed, which efficiently records all logic nodes ever created in the synthesis process. A HAIG can be constructed in a fast, memory efficient, and scalable way. It is an FSM, which contains the initial and final FSMs to be compared as well as many redundant, sequentially equivalent nodes. The sets of equivalent nodes form “bridges” connecting the initial and final machines and can be used to construct an inductive invariant. It is shown that this invariant is sufficient to prove delayed sequential equivalence between the two FSMs. The complexity of validating this is roughly the cost of one combinational SAT call of the size of the two machines; however, the many structural similarities, which are pre-identified in the HAIG structure, make the proof of invariance particularly easy and scalable.